In a move that could reshape the landscape of advanced chip packaging, Taiwan Semiconductor Manufacturing Company (TSMC) is reportedly gearing up to unveil its next-generation CoPoS (Chip-on-Panel-on-Substrate) technology. Sources familiar with the matter suggest this innovative approach will dramatically expand the size of packaging substrates, potentially reaching dimensions of 310 x 310mm or even beyond.
CoPoS represents a significant evolution of existing CoWoS-L and CoWoS-R (Chip-on-Wafer-on-Substrate) technologies, both of which utilize square substrates. The core innovation lies in the “panelization” of the interposer layer, effectively replacing traditional circular wafers with large rectangular panel substrates.
According to projections, TSMC plans to establish a pilot production line for CoPoS in 2026, followed by intensive process optimization in 2027, with the aim of mass production commencing between late 2028 and early 2029.
Similar to FOPLP (Fan-Out Panel Level Packaging), CoPoS utilizes large panel substrates for packaging. However, key distinctions exist. FOPLP bypasses the need for an interposer, with chips directly re-distributed on the panel substrate and interconnected via Redistribution Layers (RDLs).
This architecture offers advantages such as cost-effectiveness, high I/O density, and design flexibility, making it suitable for applications like edge AI, mobile devices, and mid-range ASICs.
CoPoS, on the other hand, incorporates an interposer, enabling superior signal integrity and more robust power delivery—a critical advantage for high-end products integrating GPUs and HBM (High Bandwidth Memory) chips. Moreover, interposer materials are transitioning from traditional silicon to glass, promising enhanced cost efficiencies and thermal stability. Industry analysts anticipate that CoPoS will eventually supersede CoWoS-L, with NVIDIA likely to be among the first adopters.
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