An often-overlooked aspect of semiconductor manufacturing is rapidly emerging as the critical bottleneck for the advancement of artificial intelligence. This crucial stage, known as advanced packaging, is where chips are integrated into functional hardware capable of interacting with the external world. Currently, the vast majority of this sophisticated process is concentrated in Asia, with supply struggling to keep pace with surging demand.
This deficiency is now commanding significant attention, with industry titans like Taiwan Semiconductor Manufacturing Co. (TSMC) investing heavily in new facilities in Arizona. Simultaneously, tech visionary Elon Musk is reportedly tapping Intel for its expertise in custom chip packaging for his ambitious projects, including those at SpaceX and Tesla.
“Advanced packaging could very quickly become a choke point if significant capital expenditure isn’t deployed proactively to accommodate the anticipated surge in chip fabrication output over the next few years,” warns John VerWey of Georgetown University’s Center for Security and Emerging Technology.
In a candid interview, Paul Rousseau, head of packaging solutions at TSMC North America, revealed to CNBC that the company’s advanced packaging revenues are “growing very substantially.” Their most sophisticated technique, Chip on Wafer on Substrate (CoWoS), is experiencing an astonishing 80% compound annual growth rate. AI powerhouse Nvidia has reportedly secured a significant portion of TSMC’s most advanced packaging capacity, solidifying TSMC’s leadership in this domain.
However, Intel is demonstrating technological parity. Despite facing challenges in securing major external clients for its chip fabrication services, Intel has successfully attracted significant packaging customers, including Amazon and Cisco. Musk’s recent announcement to leverage Intel for custom chip packaging at his planned Texas “Terafab” facility for SpaceX, xAI, and Tesla underscores the growing importance of this segment.
Intel’s global packaging operations are primarily located in Vietnam, Malaysia, and China, although advanced packaging processes are also conducted at U.S. facilities in New Mexico, Oregon, and Chandler, Arizona. CNBC was granted an exclusive tour of the Arizona site, offering a glimpse into the intricate operations.
The spotlight on advanced packaging intensifies as the relentless pursuit of higher density, performance, and efficiency in AI hardware pushes the boundaries of traditional chipmaking. With transistor density approaching fundamental physical limitations, innovative packaging methodologies are becoming indispensable. As Rousseau aptly puts it, “It’s really the natural extension of Moore’s Law into the third dimension.”
For decades, individual silicon dies were detached from wafers and integrated into systems for consumer electronics, automotive applications, and industrial machinery. However, the dramatic escalation in chip complexity fueled by the AI revolution has spurred the evolution of packaging. Today, advanced techniques involve co-packaging multiple dies – such as logic processors and high-bandwidth memory (HBM) – into a single, integrated unit, akin to a sophisticated graphics processing unit (GPU). Advanced packaging is the critical enabler for seamless communication between these disparate components and the broader system.
“Up until about five or six years ago, nobody was doing this,” notes Patrick Moorhead, a prominent chip analyst at Moor Insights & Strategy, adding that packaging was once an “afterthought” relegated to junior engineers. “Now, obviously, we know it’s as important as the die itself.”
### The Bottleneck Intensifies
Nvidia’s substantial commitment to TSMC’s leading-edge CoWoS technology has led to significant capacity constraints. Reports suggest that TSMC has even outsourced some aspects of the CoWoS process to specialized third-party companies like ASE and Amkor, renowned leaders in outsourced semiconductor assembly and testing. ASE anticipates its advanced packaging sales to double to $3.2 billion in 2026 and is actively expanding its operations in Taiwan.
TSMC is also bolstering its packaging capabilities with two new facilities in Taiwan, in addition to the two under construction in Arizona. Currently, all chips fabricated at TSMC’s Arizona fab are shipped to Taiwan for packaging, a logistical step that TSMC aims to streamline with its U.S. packaging sites. “To have that capability right next to the fab in Arizona is going to make their customers very happy,” observes Jan Vardaman, a leading packaging researcher at TechSearch International. This proximity is expected to drastically reduce turnaround times and associated costs.
Intel, meanwhile, is enhancing its packaging operations near its new advanced 18A chip manufacturing plant in Arizona. While Intel is yet to secure a major external client for its 18A fabrication services, Mark Gardner, head of foundry services, confirmed that the company has been serving packaging customers since 2022, including Amazon and Cisco. Nvidia’s $5 billion investment in Intel, announced after significant U.S. government funding, further signals a strategic alignment.
“Chip companies want to show the U.S. administration that they will do business with Intel, and the lower-risk path with Intel is to do packaging,” suggests Moorhead. Gardner sees advanced packaging as a potential “inroad” to attracting larger manufacturing clients, highlighting the benefits of integrated “one-stop-shop” solutions.
Musk’s ambitious Terafab project could serve as an early adopter of Intel’s integrated chip design, fabrication, and packaging capabilities, aiming to achieve an unprecedented 1 terawatt of annual compute power for AI.
### Evolving from 2D to 3D Architectures
Traditional chips, like central processing units (CPUs), often rely on 2D packaging. However, the escalating demands of complex processors, such as GPUs, necessitate more advanced solutions. TSMC’s CoWoS, a form of 2.5D packaging, addresses this by incorporating an interposer layer. This layer provides denser interconnections, enabling high-bandwidth memory to be positioned directly alongside the processing die, effectively mitigating the “memory wall” bottleneck.
“You just can’t get enough memory inside your compute chip to fully utilize it. So when we introduce CoWoS, we are able to bring the HBM memory right beside the compute in a very efficient way,” explains TSMC’s Rousseau. TSMC’s pioneering 2.5D technology, first introduced in 2012, has seen continuous refinement, with Nvidia’s latest Blackwell GPUs utilizing the cutting-edge CoWoS-L.
Intel’s primary advanced packaging technology is the Embedded Multi-Die Interconnect Bridge (EMIB). Similar to TSMC’s approach, EMIB employs silicon bridges instead of an interposer, offering a potential cost advantage by strategically placing these bridges only where needed.
Looking ahead, the industry is heavily invested in the development of 3D packaging. Intel’s Foveros Direct and TSMC’s System on Integrated Chips (SoIC) represent distinct approaches to vertically stacking chiplets. “Instead of having the chip side by side, now we put them one on top of the other,” says Rousseau, enabling them to “really behave as if they’re one chip and that provides a whole other level of performance gain.” TSMC anticipates products utilizing SoIC to reach the market within a couple of years.
Meanwhile, memory manufacturers like Samsung, SK Hynix, and Micron are already leveraging 3D packaging to stack dies for high-bandwidth memory. The race is also on to optimize interconnections. Companies are exploring hybrid bonding, a technique that replaces traditional solder bumps with copper pads for direct pad-to-pad connections. “Instead of a bump, we could do a pad-to-pad connection, which is almost no distance at all, and so that gives us better power performance,” explains Vardaman. “It also gives us better electrical performance since the shortest path is the best path.” This innovation promises to further enhance performance and efficiency as the industry navigates the complex landscape of AI hardware development.
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